Wordlines may be coupled with access transistors in memory arrangements. It may be desired to develop memory arrangements having numerous improvements; such as, for example, increased “on-current” along the wordlines, reduced leakage associated with access transistors, higher retention (less refresh rate) of memory cells coupled with the access transistors, etc. Unfortunately, it is difficult to provide such improvements while also scaling wordlines into increasingly tighter configurations associated with increasing levels of integration. Accordingly, it is desired to develop new designs which enable improvements in one or more of increased drive current, reduced leakage, increased refresh rate, etc., of highly-integrated memory arrangements.